Technical Field
The present invention generally relates to semiconductor device design and, more particularly, to designing semiconductor devices to prevent charging damage during fabrication.
Description of the Related Art
Plasma induced gate oxide damage is caused during the fabrication of an integrated circuit. Various fabrication processes, in particular those that involve plasmas, can cause a charge buildup on circuit components. This charge buildup results in a voltage being applied to the circuit components that is in excess of the tolerances of those devices. In one specific example, the buildup of charge can cause a breakdown in the gate dielectric of a transistor, thereby damaging the transistor.
Charge builds up in particular on conductors. As the area of conductors increases, for example from component interconnects, the collected charge increases and the higher the likelihood of a breakdown. Conversely, the greater the gate area, for example from multiple devices connected to the interconnect, the more the charge buildup will be spread out and the lower the likelihood of a breakdown.
To address this problem, circuit layouts are checked for compliance with design rules that establish safe margins during fabrication. These rules are referred to as “antenna rules,” and a violation of such rules is an “antenna violation.” However, in fully depleted semiconductor-on-insulator (SOI) technologies, the channel region and buried dielectric of a device are made particularly thin. While this provides certain advantages in tuning the electrical characteristics of the device (e.g., by applying a voltage to a well underneath the buried dielectric), the use of fully depleted SOI structures creates the risk of plasma induced damage to the buried dielectric as well.